Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...

Chip designs are optimized for lower cost, better performance, or lower power. The same cannot be said about verification, where today very little effort is spent on reducing execution cost, run time, ...

Evolving Verification Environments It was standard practice in the early days of hardware design to design a chip and then verify it. However this methodology started to break down in the 1980s when ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

Corporate efficiency consultants love to talk about “the dead moose on the table”—the important topic that everyone knows about but no one wants to bring up. In system-on-chip (SoC) verification, ...

Designing the hardware-software interface. Dealing with "bytes enables" in RTL verification. Automating the HSI design process across the entire dev team. The hardware-software interface (HSI) holds ...

In partnership with the Israel Tech Challenge, Apple is co-hosting an event at its Israel headquarters to discuss a new Design Verification Engineering course. This course will be a ten month-long ...

Siemens plans to integrate Aster's advanced "shift-left" design for test functionality into Siemens' Xpedition and Valor ...