EDN

Implementing floating-point DSP on FPGAs

For developers using FPGAs for the implementation of floating-point DSP functions, one key challenge is how to decompose the computation algorithm into sequences of parallel hardware processes while ...
Design-Reuse

How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs

Here we provide rational for using Centar’s floating-point IP core for the new Altera Arria 10 and Stratix 10 FPGA platforms. After a short contextual discussion section, a comparison of various FFT ...
EDN

Altera aids floating-point DSP implementation in FPGAs

Altera is quietly rolling out the ability for DSPdesigners to move directly from Simulink models to floating-point data pathsimplemented in Altera FPGAs. The capability, fully described by Altera ...
Design-Reuse

Altera Changes the Game for Floating Point DSP in FPGAs

San Jose, Calif., April 22, 2014– Altera Corporation (Nasdaq: ALTR) today changed the game as it relates to floating-point DSP performance in an FPGA. Altera is the first programmable logic company to ...