Semiconductor Engineering

Logic Synthesis Basics For FPGA

In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all ...
EDN

Getting the most out of RTL logic synthesis

As chip designers, we take register-transfer-level logical synthesis for granted today. And that's a good thing. That means that we are all comfortable with it. I remember back in the early '90s when ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
Electronic Design

Make Logic Synthesis Work For YouSponsored by: CADENCE DESIGN SYSTEMS

Think Global RTL coding style and how you drive today's synthesis tools affect your results. Take advantage of global RTL optimizations by synthesizing big blocks in top-down fashion instead of ...
Semiconductor Engineering

HW Security: Flip-Flops Along Logic Gates to Prevent Synthesis Tools’ Structural Leakages (TU Dresden, Ruhr Univ. Bochum)

A new technical paper titled “Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks” was published by researchers at TU Dresden and Ruhr ...