Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

With increased clock domains in modern ASICs, clock-domain crossing (CDC) has become ubiquitous, indispensable, and essential. Of course, timing is always an issue. High clock speeds and delays in ...

In the previous blog (Synchronization techniques for multi-clock domain SoCs& FPGAs), we studied different types of synchronization techniques to synchronize signals from one clock domain to another.

Time-sensitive networks (TSN) in Ethernet are improving computer-based measurements from sub-microsecond to sub-nanosecond precision. By using message-based protocols that synchronize clocks, it is ...

The IEEE 1588 Precision Time Protocol enables precise time synchronization over the packet-based Ethernet network so that the time on a slave clock at one end of the network agrees with a master clock ...

Many of today's system-on-chip (SoC) designs cause significant problems and delays as they go through the physical design process. Yes, physical design is harder than ever. But part of the problem is ...