EDN

Sonics Improves NoC Concurrency Management For SoC Designs With Multi-Channel Memory Sub-Systems, Addresses Place & Route Tool Restrictions

“We originally patented IMT in 2008 and it has been routinely implemented by many of our SonicsSX ® customers. At that time, SoC designers were early in the move to multi-channel memory architectures, ...
Design-Reuse

Transactional Level Modeling (TLM) of a High-performance OCP Multi-channel SDRAM Memory Controller

How the use of the OCP TLM SystemC library enhanced the design process of an OCP-based SDRAM controller IP, and dramatically improved the customer evaluation process. Introduction As a leading ...
Semiconductor Engineering

A Practical DRAM-Based Multi-Level PIM Architecture For Data Analytics

A technical paper titled “Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics” was published by researchers at Korea Advanced Institute of Science & Technology (KAIST ...
Design-Reuse

Sonics Eliminates Barriers to Multichannel Memory Management Industry Adoption With New Interleaved Multichannel Technology(TM)

MILPITAS, Calif. -- July 1, 2008 -- Sonics Inc., a premier supplier of system-on-chip SMART Interconnect solutions, today announced the availability of Interleaved Multichannel Technology (IMT), a ...
Ars Technica

Mixing different brands of ECC RAM in multi-CPU systems

I have read on various forums that mixing memory modules of different brands can lead to stability issues even though the timings and voltages are the same. If I understand it correctly, each CPU ...
Electronic Design

Memory Channel Storage Puts SSD Next To CPU

Diablo Technologies TeraDIMM changes how systems can access flash storage by putting it on the DRAM memory channels eliminating the bottlenecks imposed by other disk and system interfaces typically ...