EDN

Putting the R in RTL : Coding Registers in Verilog and VHDL

Many years ago, when I was a young man and the Boston Red Sox had just lost the 1986 world series, controversy stalked the land of hardward development. A new technology called Register Transfer ...
EDN

SystemVerilog reference verification methodology: RTL

SystemVerilog enables such a unified approach, since code coverage, functional coverage points, and assertions are all defined by the same language. Using formal analysis The VMM for SystemVerilog ...
Design-Reuse

How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 2

As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog. Enhance ...
Design-Reuse

Concept Engineering Introduces RTLvision PRO to Help Designers of IP-based System-on-Chip Reach Faster RTL Code Closure

FREIBURG, Germany - July 6, 2006 - Concept Engineering today announced the release of RTLvision¢â PRO, a customizable tool to help designers of intellectual property (IP)-based system-on-chip reduce ...
Electronic Design

SystemVerilog: The Complete Solution

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

One of the beautiful things about SystemVerilog is that its verification capabilities can be adopted incrementally. One needn't swallow the entire language at once to make use of a given set of ...
Dataquest

Cocotb verification in python can turbo-charge chip development!

Cocotb is a COroutine-based COsimulation TestBench environment for verifying VHDL and SystemVerilog RTL using python. Using open source, it will allow HDL code to bind with python code using VPI or ...