At Alcatel-Lucent, we test chassis-level products that provide 42 board slots on a midplane, essentially a passive backplane that accepts boards on its front and rear sides. Thirty-four of those slots ...

As design size and complexity increase, so too does the cost of test. Both the design community and the test industry are looking at various approaches to lower the cost of manufacturing test. This ...

For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...

Yield improvement at sub 100-nm technologies relies on the latest scan test techniques. As IC feature sizes shrink below 90 nm, in-line inspection techniques to determine yield-limiting problems ...

Some new design-for-test (DFT) technologies are difficult, expensive, or risky to implement but offer significant benefits. Other technologies are easy to implement but offer minor improvements. The ...

Tessent Streaming Scan Network (SSN) is a system for packetized delivery of scan test patterns. It enables simultaneous testing of any number of cores with few chip-level pins, and reduces test time ...