ALLENTOWN, Pa. — Agere Systems is working with San Jose, California-based Cadence Design Systems Inc. to provide Agere ASIC customers with access to Cadence's “First Encounter” EDA software. This is ...

Socionext used the Cadence full-flow digital and signoff tools for the successful production tapeout of its latest large, 16nm ASIC chip.

Cadence announced Global Unichip Corporation (GUC) used the Cadence digital full flow to accelerate the time to tapeout of its ASIC designs.

In the RF domain, Cadence and Samsung have demonstrated an advanced co-design flow for Front-End Module (FEM) and Antenna-in-Package (AiP) designs targeting mmWave applications.

SAN JOSE, Calif. -- Jan 10, 2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, today announced significant new advancements to help boost ...

Cadence Design Systems and Fujitsu Microelectronics America (FMA) have announced that FMA is shipping initial production volumes of a new, complex, structured ASIC using Cadence Encounter IC ...

Cadence Design Systems, Inc. collaborated with TSMC to develop a node-to-node design migration flow built upon the Cadence ® Virtuoso ® design platform for custom/analog IC blocks that use TSMC ...

Cadence Design Systems, Inc. CDNS recently announced that its flagship enterprise emulation verification platform — Palladium Z1 — has been deployed by Acacia Communications, Inc. to design ...