Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief ...

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...

Discover how this powerful open-source SPICE simulator helps you analyse and validate analog, digital and mixed-signal ...

Evolving Verification Environments It was standard practice in the early days of hardware design to design a chip and then verify it. However this methodology started to break down in the 1980s when ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant Challenges facing chip design verification engineers are ...

Designing the hardware-software interface. Dealing with "bytes enables" in RTL verification. Automating the HSI design process across the entire dev team. The hardware-software interface (HSI) holds ...

In partnership with the Israel Tech Challenge, Apple is co-hosting an event at its Israel headquarters to discuss a new Design Verification Engineering course. This course will be a ten month-long ...

I'm fast approaching the one year mark with my current employer since I graduated last year. Previously, I did three four month work terms with them and they were for the most part interesting. I took ...